1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device which is provided with a mode for performing a functional test of circuit blocks formed in an integrated circuit.
2. Description of Related Art
Known types of integrated circuits in semiconductor devices include those that are a consolidation of a plurality of large-scale macro cells. Macro cells are circuit blocks constituted by combining a plurality of small-scale circuit blocks which have already been individually designed. For example, macro cells are employed as RAM (random access memory) blocks or the like.
In the case of employing macro cells in integrated circuits, a functional test of only this macro cell is sometimes performed in the testing process of the semiconductor device. For this reason, some integrated circuits are provided with circuits for a functional test of macro cells.
In general, a functional test of macro cells comprises the testing of access time and the testing of setup time.
Access time is the required time from when the signal input terminal of the macro cell receives the signal until the signal output terminal outputs the signal. When access time is longer than the designed value, the next stage circuit cannot be caused to operate properly. The signal input terminal inputs the signal at a timing of clock is input (rise timing or fall timing). Consequently, the access time may be measured by measuring the required time from when the clock input terminal receives the clock until the signal output terminal outputs the signal.
Setup time is the allowable time difference from when the signal potential is applied to the signal input terminal until the clock is input to the clock input terminal, and the allowable time difference from when the clock is input to the clock input terminal until the application of the signal potential to the signal input terminal is ended. In order for the macro cell to correctly receive a signal, the time difference from when the signal potential is applied to the signal input terminal until the clock is input to the clock input terminal must be greater than or equal to a prescribed allowable time difference. Likewise, in order for the macro cell to correctly take up a signal, the time difference from when the clock is input to the clock input terminal until the application of the signal potential to the signal input terminal is ended must be greater than or equal to a prescribed allowable time difference. When these allowable time differences are greater than the designed values, there is a risk that a signal of erroneous value will be taken up by the macro cell. For this reason, in the testing of setup time, it is determined whether the signal is read correctly in the case where the time difference of the start/end timing of signal application and clock input timing is a prescribed value. The output signal value is used to determine whether the signal was read correctly.
In conventional semiconductor devices, the required time from when a test signal is input to the input pad of the chip until the output pad of the chip outputs the signal is measured in the case of testing access time. Also, in the case of testing setup time, the value of the output signal is read for when a prescribed value is established for the difference between the start/end time of applying a test signal to the input pad of the chip and the time of the application of the test clock to the clock input pad of the chip.
However, in the case of a long wiring distance between these bonding pads and the macro cells, the wiring delay cannot be ignored and accurate a functional test cannot be performed. In the access time testing discussed above, for example, an accurate determination cannot be made in the case where it is impossible to ignore the wiring delay between the input pad and the signal input terminal of the macro cell and the wiring delay between the signal output terminal of the macro cell and the output pad. Also, in the setup time testing discussed above, an accurate determination cannot be made in the case where it is impossible to ignore the difference between the wiring delay from the input pad to the signal input terminal of the macro cell and the wiring delay from the clock input pad to the clock input terminal of the macro cell.